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at The Institute of Energy Conversion Generic critical technical issues in thin film solar cell technology
Technical status of specific thin film technologies The critical issues that need to be addressed to support the development of viable commercial processes and to improve the module performance for the specific materials are:CuInSe2 has a bandgap of 1 eV and the devices typically have open circuit voltage (Voc ) less than 0.5 V. This bandgap is about 0.5 eV less than required for a single junction device to have optimal efficiency for terrestrial applications. Further, the high short circuit current (Jsc) of these devices reduces module performance because of larger active area and series resistance losses, and because devices with low Voc typically suffer larger fractional losses as the devices are operated under real PV module operating conditions (module operating temperatures of 50 to 60 C) as compared to operation under standard measurement conditions (25 C). Solar cells based on CuInSe2 have been made at IEC and elsewhere with bandgaps of about 1.2 eV through the addition of Ga, leading to efficiencies greater than 15% . The CuIn1-xGaxSe2 cells with record-level efficiencies have been produced by reacting the absorber layers at temperatures above 500 C. Such high processing temperatures limit the choice of substrate materials (e.g., excluding use of lightweight flexible Kapton foil) and make processing and substrate handling in general more difficult. It is presently not well understood why the champion cells had to be processed at such high temperatures. Also, it is desirable to further increase the bandgap to 1.4 to 1.6 eV for improved module performance. This can be accomplished by increasing the Ga content or by adding S as an additional alloy component. Amorphous Silicon (a-Si) PV modules were the first thin-film PV modules to be commercially produced and are presently the only thin-film technology that has had an impact on the overall PV markets. However, the efficiencies of these modules have not yet reached levels that were predicted in the 1980's. To a significant degree this is due to the intrinsic degradation of a-Si under illumination. The amount of light-induced degradation can be limited to 20% in modules operating under outdoor conditions. Both material processing schemes and device design schemes have been developed to improve the stabilized solar cell efficiency of a-Si solar cells. The use of multi-bandgap multijunction devices (allowing the use of thinner absorber layers in the component cells) and the use of light-trapping appear to be the most powerful device design techniques to improve stabilized device performance. Presently, champion cells have stabilized efficiencies of 12% and champion modules (1 square foot) have stabilized efficiencies of over 10%. The US industry is currently using two approaches to build a-Si-based modules. Substrate type devices are built on stainless steel foil which has been first covered with a textured back reflector while superstrate type devices are built on glass coated with transparent conductors (TCO.) The texture and transparency of the TCO contacts are critical to improve light-trapping and Jsc. Reducing optical losses in the TCO will allow thinner i-layers to generate the same Jsc, thus improving stability. However, the goal for all high efficiency a-Si device designs is maximizing the optical enhancement (light trapping) and minimizing the light-induced degradation. The national university/industry/NREL amorphous silicon program has broken down the optimization of stabilized cell performance into four team areas: three teams dealing with the individual high-, mid-, and low-bandgap component cells, and a fourth dealing with overall generic issues of optical enhancement, contacts, substrates, and power matching of the multijunction device. However, the optimization of two-terminal dual- or triple-junction cells has further requirements such as to minimize the electrical and optical losses in the internal p/n junctions (sometimes called tunnel junctions) and in the TCO and substrates. The p and n layers of a cell have to be optimized not only to result in optimum performance of the component cells, but also to give the lowest losses in multi-junction devices. Instability of CdTe-based solar cells and modules is commonly assumed to be related to the rear contact, especially if this contact is Cu-doped. There is a need to further develop a stable ohmic contact for CdTe compatible with monolithic integration technologies. New contacts must be tested and a method developed to rapidly characterize stability. It appears likely that the optimization of such a contact depends also on the details of the other layers used in the device (CdTe, CdS, SnO2, type of glass). The effects of high temperature processing, either during deposition or after film growth, and CdCl2 treatments on the operation of the device are not well characterized. Of particular concern is the uniformity of large-area modules and the "robustness" of such processes. Questions concerning CdS-CdTe interdiffusion, O and Cl doping, and chemical reactions between CdCl2 and CdTe need to be addressed quantitatively. Although many researchers have produced devices with 12% efficiency, few have exceeded 14%. The challenge is to obtain high values for Jsc without loss of Voc, and a good spectral response at short wavelengths (l<500 nm) without sacrificing the spectral response at longer wavelengths. It is important to understand how various process conditions are related to these losses in Voc and Jsc. It has been established that solar cell parameters are sensitive to the details of the CdS/CdTe interface. Understanding the mechanisms in detail would accelerate device optimization, which is finally realized to be an interactive process. Thus, the optimization of each layer in the device depends on the processing of all the other layers present. One approach to lower the cost of today's crystalline or multicrystalline Si wafer-based solar modules is to fabricate thin Si layers on a low cost substrate. These thin Si devices will be 10-30 microns thick, which is ten times thinner than presently available Si wafers. Besides using less raw material, they will be processed at lower temperatures which also reduces manufacturing costs. To date, thin Si materials have had poorer electronic properties compared to the more expensive Si wafers, partly due to impurity interaction with the foreign substrate and partly due to imperfect crystallinity and structural defects. Thin Si devices will require light trapping to maximize the absorption in the relatively thinner layers. Key requirements for such devices are a process which yields Si films with large grain size (>100 m) and good electronic properties deposited at a high growth rate (>50 Å/sec) on a low cost substrate which allows light trapping. |
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